Search - dsp fpga

[VHDL-FPGA-Verilog] fpga_ver

Description: Altera StratixII FPGA与DSP TS201实现总线通信的程序，Verilog实现-Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization
Platform: | Size: 8059904 | Author: 路永轲 | Hits:

[VHDL-FPGA-Verilog] emifa_ram

Description: FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
Platform: | Size: 2048 | Author: jijie | Hits:

[Documents] FPGAPDSP

Description: 基于FPGA+DSP的雷达信号处理模块的设计-Based FPGA+DSP radar signal processing module
Platform: | Size: 253952 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA2-DSP2-EDMA

Description: 例程是FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners
Platform: | Size: 206848 | Author: liu | Hits:

[Software Engineering] Image-Compress-FPGA_DSP

Description: 比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.-More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.
Platform: | Size: 106496 | Author: LEI GUOWEI | Hits:

[Documents] andmulti-PCI9656-

Description: 基于FPGA的PCI9656与多DSP的接口设计-Interface design of FPGA-based DSP andmulti-PCI9656
Platform: | Size: 272384 | Author: 冷灵气 | Hits:

[Software Engineering] Radar-Signal-Processing

Description: 一些关于雷达系统硬件电路设计，数字滤波设计及FPGA/DSP等设计的文章，对初学者很具有参考意义。-Some articles about the radar system hardware circuit design, digital filter design and FPGA/DSP, such as design, it is a reference for the beginner.
Platform: | Size: 14240768 | Author: 南煎丸子 | Hits:

[Program doc] Pradeep-N

Description: PCIE between altera DSP and FPGA
Platform: | Size: 12288 | Author: pradeep | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 把32位的数据转换成8位数据输出，用做fpga把数据传给dsp处理-The 32-bit data into 8 bits of data output
Platform: | Size: 842752 | Author: 程钗 | Hits:

[Program doc] Introduction-to-Network-Simulator-NS2-1

Description: The vector Received contains the noisy output samples from the analog front-end. I In a real system, these samples would be processed by digital hardware to recover the transmitted bits. I Such digital hardware may be an ASIC, FPGA, or DSP chip. I The first function performed there is digital matched
Platform: | Size: 4113408 | Author: mk | Hits:

[matlab] _9b4ca76dcb513a53aa647a9ccf41ecb8

Description: 混沌的数值仿真主要包括MATLAB编程、SIMULINK模块构建、EWB仿真以及其他一些相关的软件仿真或数值计算等方法，从而获取混沌吸引子的相图、时域波形图、李氏指数、分叉图和功率谱等。混沌的硬件实验主要包括模拟/数字电路设计与硬件实验、现场可编程门阵列器件（FPGA）、数字信号处理器（DSP）等硬件实现方法来产生混沌信号。本节仅对各种数值仿真方法作简单介绍。- Chaos numerical simulation including MATLAB programming, SIMULINK module build, EWB simulation and other related software simulation or numerical calculation methods, in order to gain chaotic attractor phase diagram, time-domain waveform, Lipschitz exponent, bifurcation diagrams and power spectrum. Chaos experiment hardware includes analog/digital circuit design and hardware experiments, field-programmable gate array device (FPGA), digital signal processor (DSP) hardware implementation to generate chaotic signals. This section is only a variety of numerical simulation methods for a brief introduction.
Platform: | Size: 154624 | Author: 闵国旗 | Hits:

[Embeded-SCM Develop] echo_dj

Description: verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
Platform: | Size: 5120 | Author: arourd | Hits:

[VHDL-FPGA-Verilog] arm

Description: 此程序是ARM+FPGA的总线通信程序，我只提供FPGA这一边的，其实我现在把这个程序移植到dsp+cpld上面去了，那个程序其实都出不多-This program is ARM+ FPGA bus communication procedures, I only FPGA side, in fact, I now put this program ported to dsp+ cpld go above, and that the program actually much
Platform: | Size: 2048 | Author: meng219902 | Hits:

[VHDL-FPGA-Verilog] 6f041ed721eb

Description: 简单的dsp与fpga接口代码。emif-Dsp and fpga simple interface code. emif
Platform: | Size: 1147904 | Author: ninny | Hits:

[Other] GPS-Power-Inversion-Algorithm

Description: 实现了基于功率倒置算法的 GPS 抗干扰实时系统，并且提出了一种低复杂度的实现算法。运用 Xilinx 公司的 Virtex-4 以及 TI 公司的 TMS320C6416T 硬件平台，采用双 FPGA+ 单 DSP 结构来实现整个算法。实验结果表明， GPS 信号经过实时抗干扰系统处理后，可以运用普通的接收机进行实时、精确的定位。该系统具有兼容性好、精度高等优点。-Based on power inversion algorithm，a GPS real-time anti-jamming system composed of the Virtex-4 and TMS320C6416T hardware platform has been finished. In addition， an improved method which is easy to implement is also proposed. The algorithm is implemented on the architecture which is made up of double FPGA+DSP. Experimental results show that the target position which can′t be found without anti-jamming will be located precisely with ordinary receivers after the GPS signals with blanketing jamming have been passed through our real-time anti-jamming system. Lots of advantages lies in this system such as：good compatibility， accurate positioning etc.
Platform: | Size: 336896 | Author: 刘金强 | Hits:

[ARM-PowerPC-ColdFire-MIPS] LED

Description: 开发板（demoboard）是用来进行嵌入式系统开发的电路板，包括中央处理器、存储器、输入设备、输出设备、数据通路/总线和外部资源接口等一系列硬件组件。开发板一般由嵌入式系统开发者根据开发需求自己订制，也可由用户自行研究设计。开发板是为初学者了解和学习系统的硬件和软件，同时部分开发板也提供的基础集成开发环境和软件源代码和硬件原理图等。常见的开发板有51、ARM、FPGA、DSP开发板。-Hardware and software learning system, while basic integrated development environment and software source code and hardware schematics part of the development board, etc. are also provided.
Platform: | Size: 31744 | Author: ge zhenmin | Hits:

[ARM-PowerPC-ColdFire-MIPS] Chuankoou1

Description: 开发板（demoboard）是用来进行嵌入式系统开发的电路板，包括中央处理器、存储器、输入设备、输出设备、数据通路/总线和外部资源接口等一系列硬件组件。开发板一般由嵌入式系统开发者根据开发需求自己订制，也可由用户自行研究设计。开发板是为初学者了解和学习系统的硬件和软件，同时部分开发板也提供的基础集成开发环境和软件源代码和硬件原理图等。常见的开发板有51、ARM、FPGA、DSP开发板。-Hardware and software learning system, while basic integrated development environment and software source code and hardware schematics part of the development board, etc. are also provided.
Platform: | Size: 31744 | Author: ge zhenmin | Hits:

[ARM-PowerPC-ColdFire-MIPS] K60kanmenggou

Description: 开发板（demoboard）是用来进行嵌入式系统开发的电路板，包括中央处理器、存储器、输入设备、输出设备、数据通路/总线和外部资源接口等一系列硬件组件。开发板一般由嵌入式系统开发者根据开发需求自己订制，也可由用户自行研究设计。开发板是为初学者了解和学习系统的硬件和软件，同时部分开发板也提供的基础集成开发环境和软件源代码和硬件原理图等。常见的开发板有51、ARM、FPGA、DSP开发板。-Hardware and software learning system, while basic integrated development environment and software source code and hardware schematics part of the development board, etc. are also provided.
Platform: | Size: 32768 | Author: ge zhenmin | Hits:

[Embeded-SCM Develop] echo_dj

Description: verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
Platform: | Size: 5120 | Author: chaoxin | Hits:

[Software Engineering] rida

Description: 雷达信号分选算法研究及硬件设计实现-本文详细介绍了利用高性能FPGA——-virtex4 和DSP——TMS320C64 16T芯片搭建硬件平台，协同处理实现雷达信号分选的电路，根据电路特点设计了一套完整的分选算法.-he sorting of radar signal
Platform: | Size: 3762176 | Author: john | Hits:

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[VHDL-FPGA-Verilog] fpga_ver

[VHDL-FPGA-Verilog] emifa_ram

[Documents] FPGAPDSP

[VHDL-FPGA-Verilog] FPGA2-DSP2-EDMA

[Software Engineering] Image-Compress-FPGA_DSP

[Documents] andmulti-PCI9656-

[Software Engineering] Radar-Signal-Processing

[Program doc] Pradeep-N

[VHDL-FPGA-Verilog] verilog

[Program doc] Introduction-to-Network-Simulator-NS2-1

[matlab] _9b4ca76dcb513a53aa647a9ccf41ecb8

[Embeded-SCM Develop] echo_dj

[VHDL-FPGA-Verilog] arm

[VHDL-FPGA-Verilog] 6f041ed721eb

[Other] GPS-Power-Inversion-Algorithm

[ARM-PowerPC-ColdFire-MIPS] LED

[ARM-PowerPC-ColdFire-MIPS] Chuankoou1

[ARM-PowerPC-ColdFire-MIPS] K60kanmenggou

[Embeded-SCM Develop] echo_dj

[Software Engineering] rida

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